A computer bus is a communication link used to connect multiple computer subsystems. For example, a computer bus is used to link the memory and processor, and to link the processor with input/output (I/O) devices. Computer buses are traditionally classified as follows: processor-memory buses, I/O buses, or backplane buses. Processor-memory buses are short, generally high speed, and matched to the memory system so as to maximize memory-processor bandwidth. I/O buses, by contrast, can be lengthy, can have many types of devices connected to them, and often have a wide range in the data bandwidth of the devices connected to them. Backplane buses are designed to allow processors, memory, and I/O devices to coexist on a single bus. Backplane buses balance the demands of processor-memory communication with the demands of I/O device-memory communication. Backplane buses received their name from the fact that they are typically built into a computer backplane--the fundamental interconnection structure within the computer chassis. Processor, memory, and I/O boards plug into a backplane and then use the backplane bus to communicate.
Processor-memory buses are often design-specific, while both I/O buses and backplane buses are frequently standard buses with parameters established by industry standards. The distinction between bus types is becoming increasingly difficult to specify. Thus, the present application generically refers to computer buses to encompass all processor-memory buses, I/O buses, and backplane buses.
The problem with computer buses is that they create a communication bottleneck since all input/output must pass through a single bus. Thus, the bandwidth of the bus limits the throughput of the computer. Physical constraints associated with existing computer buses are beginning to limit the available performance improvements generally available in computers.
The physical operation and constraints of existing computer bus designs are most fully appreciated with reference to FIG. 1. FIG. 1 illustrates a computer bus 20 positioned on a backplane 22. The computer bus 20 is a set of wires, effectively forming a transmission line. A random number of system cards (or cards) 24A-24N are attached to the computer bus 20. By way of example, the cards 24 may include a video processing card, a memory controller card, an I/O controller card, and a network card. Each card 24 is connected to the computer bus 20 through a connector 26. Thus, each card 24 is electrically connected to the set of wires forming the computer bus 20. As a result, one card, say card 24A, can communicate with another card, say 24N, by writing information onto the computer bus 20. Only one card 24 can write information onto the computer bus 20 at a time, thus a computer bus 20 can generate a performance bottleneck as different cards 24 wait to write information onto the bus 20.
Another problem associated with a traditional computer bus 20, as shown in FIG. 1, is that its performance is constrained by complicated electrical phenomenon. For example, the connectors 26 effectively divide the bus into transmission line segments, resulting in complicated transmission line effects. Note that the transmission line segments will vary depending upon the number of cards 26 connected to the bus 20. This periodic loading of the bus 20 makes it difficult to optimize bus performance. In addition, each connector 26 produces a lumped discontinuity with parallel capacitance and series inductance, thereby complicating the electrical characteristics of the bus 20. Note also that "T-connections" are formed between the wires of a computer bus 20 and the wires to a connector 26. The T-connections complicate the electrical characteristics of the computer bus 20.
Each card 24 includes a transceiver circuit 28 connected to a card logic circuit 30, which performs the functional operations associated with the card 24. The transceiver circuit 28 is used to read and write information on the bus 20. That is, the transceiver circuit 28 reads information from the bus 20, the card logic circuit 30 processes the information, and then the transceiver circuit 28 writes processed information to the bus 20. Additional electrical complications arise with the transceiver circuits 28. For example, transmission line segments are formed between each connector 26 and each bus transceiver 28 circuit. In addition, the transceiver circuits 28 present an impedance at their package pins that depends upon the circuit design, the electrical state of the transceiver, and the packaging.
In sum, the computer bus 20 constitutes a transmission line with complicated electrical interactions caused by such factors as transmission line segments and connectors forming lumped discontinuities with parallel capacitance and series inductance. The bus 20 may be terminated with termination resistors (R) to reduce transmission line effects, such as reflections and mismatches. Nevertheless, solutions of this sort do not overcome all transmission line problems associated with a computer bus 20.
Given these complicated electrical interactions, signals on the bus 20 do not experience a uniform rise. That is, if the bus 20 was a perfect transmission line, then high signals (digital ONES) written to the bus 20 would experience a uniform rise. However, in view of the complicated electrical interactions on the bus 20, high signals frequently experience one or more spurious signal transitions before reaching a final peak value that can be processed. Waiting for signals to settle causes delays.
Another problem is that the complicated electrical interactions on the computer bus 20 require higher powered drive signals, and thus more power dissipation.
It is difficult to avoid these problems by changing the electrical characteristics of the bus 20. That is, it is difficult to design a bus with improved transmission line properties in view of the complicated factors that establish bus 20 performance. Thus, it would be highly desirable to design a new type of bus whose performance is not contingent upon complicated transmission line effects associated with prior art buses.